1. Field of the Invention
The present invention relates to flip-flops, and more particularly, to a complementary pass transistor based flip-flop (CP flip-flop) which is smaller than a conventional low-power flip-flop, and is operable at a high speed in an active mode with reduced power consumption and can latch data in a sleep mode with minimum power consumption.
2. Description of the Related Art
FIG. 1A is a circuit diagram of a conventional transmission gate master-slave flip-flop (TGFF). Referring to FIG. 1A, the FGFF consists of a master stage on the left of a dashed line and a slave stage on the right of the dashed line. When a clock signal Clk is high, the master stage receives and latches input data, and the slave stage latches and outputs the previous logic state. When the clock signal Clk is low, the master stage no longer receives the input data, and the slave stage receives and outputs the logic state passed from the master stage. In FIG. 1A, Vdd denotes a high supply voltage, GND denotes ground voltage, Clkb denotes an inverted clock signal, and Q denotes a positive output node.
FIG. 1B is a circuit diagram of a conventional hybrid latch flip-flop (HLFF). Referring to FIG. 1B, the HLFF consists of a dynamic front stage on the left of a dashed line and a static back stage on the right of the dashed line.
When a clock signal Clk goes from a high level to a low level, an inverted clock signal Clkb is delayed by three inverters. During the delay period, input data Data is passed to the front stage, and the front stage is charged or discharged, or remains at the previous logic state. The back stage remains at the previous logic state.
When the clock signal Clk goes from a low level to a high level, the front stage no longer receives the input data Data, and the back stage outputs the previous logic state.
FIG. 1C is a circuit diagram of a conventional semi-dynamic flip-flip (SDFF). Referring to FIG. 1C, the SDFF consists of a precharge stage on the left of a dashed line, and an output buffer stage on the right of the dashed line. When an input data Data is high, the precharge stage is fully discharged so that an output Q_b becomes high. When the input data Data is low, the precharge stage is charged to a logic high state, and the output Q_b becomes low.
FIG. 1D is a circuit diagram of a conventional sense amplifier flip-flop (SAFF). Referring to FIG. 1D, for the SAFF, when a clock is high, a voltage level of the input signal Data is stored in a latch circuit including two NAND gates and then is output. When the clock is low, outputs Q and Qb remain at the previous state regardless of the state of the input signal Data received.
In the conventional flip-flops described above, the master stage or the dynamic front stage needs to be precharged so that power consumption is considerable. Currently available systems need high-speed and low power consumption. However, use of the conventional flip-flops increases layout area and power consumption.
When a multi-threshold complementary metal oxide silicon (MTCMOS) technique is applied to the conventional flip-flops, the conventional flip-flops are available in the active and sleep modes of a system which includes a power-down circuit that suspends operation by cutting off the supply power. In this case, there is a need for a circuit for retaining latched data when the supply power is cut off. In addition, there is a drawback in that designing control signals for data storage is more complicate.
According to the MTCMOS technique, a MOS switch having a relatively high threshold voltage is serially connected between the power supply voltage Vdd, Vss, or GND and a logic circuit. Depending on whether the MOS switch is opened or closed, the power supply voltage is supplied to the logic circuit, which is formed by an NMOS transistor having a relatively low threshold voltage, or is cut off, thereby reducing power consumption. In particular, in the active mode, the MOS switch is turned on to supply the power supply voltage to the logic circuit. In the sleep mode, the MOS switch is turned off to stop the supply power being provided to the logic circuit, thereby minimizing power consumption of the overall system.
The MTCMOS technique is highly effective to reduce power consumption by circuits in a system in which the sleep mode is relatively longer than the active mode. However, if a special measure for the power cut-off period is not considered, data stored in a latch circuit or a flip-flop would be lost.
To solve the above-described problems, it is a first object of the present invention to provide a complementary pass transistor based flip-flop (CP flip-flop) which has a smaller layout area than a conventional low-power flip-flop and is operable at a high speed with reduced power consumption.
It is a second object of the present invention to provide a CP flip-flop in which data can be latched in the sleep mode without need for an additional circuit for retaining latched data, and power consumption is also minimized.
To achieve the first object of the present invention, there is provided a complementary pass transistor based flip-flop comprising: a clock delay unit for inverting and delaying a clock signal; a switch unit for switching input data in response to the clock signal and an output signal of the clock delay unit; and a latch unit for latching at least one output signal of the switch unit.
In a first embodiment of the CP flip-flop, the clock delay unit may include an odd number of inverters connected in series for inverting the clock signal. The switch unit may include a first switch for switching the input data in response to the clock signal, and a second switch for switching an output signal of the first switch in response to the output signal of the clock delay unit. The latch unit may include a first inverter having an input port connected to the second switch of the switch unit, and a second inverter having an input port connected to an output port of the first inverter and an output port connected to the input port of the first inverter.
In a second embodiment of the CP flip-flop, the CP flip-flop may further comprise a first inverter for inverting the input data. The clock delay unit may include an odd number of inverters connected in series for inverting and delaying the clock signal. The switch unit may comprise: a first switch for switching the input data in response to the clock signal; a second switch for switching an output signal of the first switch in response to the output signal of the clock delay unit; a third switch for switching an output signal of the first inverter in response to the clock signal; and a fourth switch for switching an output signal of the third switch in response to the output signal of the clock delay unit. The latch unit may comprise a second inverter having an input port connected to the second switch of the switch unit and an output port connected to the fourth switch; and a third inverter having an input port connected to the fourth switch of the switch unit and an output port connected to the second switch.
In a third embodiment of the CP flip-flop, the clock delay unit inverts and delays the clock signal in response to an enable signal. The switching unit may include a first switch for switching the input data in response to the clock signal and a second switch for switching an output signal of the first switch. The latch unit may include a logic circuit and a latch circuit. The logic circuit may include a NAND gate that responds to a set signal and a reset signal. The latch circuit may include first and second inverters for latching the input data and four NMOS transistors that respond to a set signal and a reset signal.
In a fourth embodiment of the CP flip-flop, the CP flip-flop may further include a first inverter for inverting the input data. The clock delay unit may invert and delay the clock signal in response to an enable signal. The switch unit may include: a first switch for switching the input data in response to the clock signal; a second switch for switching an output signal of the first switch in response to the output signal of the clock delay unit; a third switch for switching an output signal of the first inverter in response to the clock signal; and a fourth switch for switching an output signal of the third switch in response to the output signal of the clock delay unit. The latch unit may include a logic circuit and a latch circuit. The logic circuit may include a NAND gate that responds to a set signal and a reset signal. The latch circuit may include second and third inverters for latching the input data and four MOS transistors that respond to the set and reset signals.
To achieve the second object of the present invention, there is provided a CP flip-flop comprising first and second virtual power supply units, a clock delay unit, a switch unit, and a latch unit. The first virtual power supply unit provides a first virtual power supply voltage by receiving a first power supply voltage having a highest voltage level. The second virtual power supply unit provides a second virtual power supply voltage by receiving a second power supply voltage having a lowest voltage level. The clock delay unit receives and outputs a clock signal by inverting and delaying the clock signal, and further receives at least one control signal and outputs the clock signal by inverting and delaying the clock signal in response to the control signal. The switch unit switches input data in response to the clock signal and an output signal of the clock delay unit. The latch unit latches at least one output signal of the switch unit.
Both the clock delay unit and the switch unit comprise low-threshold MOS transistors, the latch unit comprises a plurality of low-threshold MOS transistors or comprises a plurality of low-threshold MOS transistors and at least one high-threshold MOS transistor. The plurality of low-threshold MOS transistors are operated between the first power supply voltage and the second power supply voltage, between the first power supply voltage and the second virtual power supply voltage, between the first virtual power supply voltage and the second power supply voltage, or between the first virtual power supply voltage and the second virtual power supply voltage, and the high-threshold MOS transistor is operated between the first,power supply voltage and the second power supply voltage. Each of the plurality of low-threshold MOS transistors has a lower threshold voltage than the high-threshold MOS transistor. For example, each of the plurality of low-threshold MOS transistors has a threshold voltage of 0.1-0.4 volts for NMOS transistors and xe2x88x920.1-xe2x88x920.4 volts for PMOS transistors, and the high-threshold MOS transistor has a threshold voltage of 0.4-0.7 volts for NMOS transistors and xe2x88x920.4-xe2x88x920.7 volts for PMOS transistors.
Preferably, each of the plurality of low-threshold MOS transistors has a threshold voltage of 0.33xc2x10.04 volts for-NMOS transistors and xe2x88x920.40xc2x10.04 volts for PMOS transistors, and the high-threshold MOS transistor has a threshold voltage of 0.6xc2x10.06 volts for NMOS transistors and xe2x88x920.65xc2x10.06 volts for PMOS transistors.
In a fifth embodiment of the CP flip-flop according to the present invention, the clock delay unit may include an odd number of inverters connected in series and each including a low-threshold MOS transistor. The switch unit may comprise: a first switch including at least one low-threshold MOS transistor for switching the input data in response to the clock signal; and a second switch including at least one low-threshold MOS transistor for switching an output signal of the first switch in response to the output signal of the clock delay unit. The latch unit may comprise: a first inverter including high-threshold MOS transistors and having an input port connected to an output port of the second switch; and a second inverter including high-threshold MOS transistors and having an input port connected to an output port of the first inverter and an output port connected to the input port of the first inverter. The latch unit may further comprise a first low-threshold PMOS transistor having one end connected to the first supply power voltage, the other end connected to the input port of the first inverter, and a gate connected to the output port of the first inverter.
In the fifth embodiment and following sixth through tenth embodiments, it is preferable that the low-threshold MOS transistors are operated between the first virtual power supply voltage and the second virtual power supply, and the high-threshold MOS transistor is operated between the first power supply voltage and the second power supply voltage.
In a sixth embodiment of the CP flip-flop according to the present invention, the clock delay unit may include a third inverter for inverting the clock signal, a fourth inverter for inverting an output signal of the third inverter, and a NOR gate for inverting the clock signal and outputting an inverted clock signal in response to an output signal of the fourth inverter and an anti-floating signal. The third and fourth inverters include low-threshold MOS transistors, and the NOR gate includes low-threshold and high-threshold MOS transistors. The same switch unit and latch unit as in the fifth embodiment are applied. The anti-floating signal prevents occurrence of leakage current by turning off the NMOS transistors 1122 and 1124 of FIGS. 11 through 14 when the power is turned off.
In a seventh embodiment of the present invention, the CP flip-flop may further include a third inverter for inverting the input data. The clock delay unit may include an odd number of inverters each having low-threshold MOS transistors. The switch unit may include a first switch for switching the input data in response to the clock signal, a second switch for switching an output signal of the first switch in response to the output signal of the clock delay unit, a third switch for switching an output signal of the third inverter, which is an inverted version of the input data, in response to the clock signal, and a fourth switch for switching an output signal of the fourth switch. Each of the first through fourth switches includes at least one low-threshold MOS transistor.
In this case, the latch unit may include: a first inverter having an input port to which an output signal of the second switch is applied and an output port connected to an output port of the fourth switch; and a second inverter having an input port to which an output signal of the fourth switch is applied and an output port connected to an output port of the second switch. Each of the first and second inverters may include high-threshold MOS transistors.
The latch unit may further comprise a first low-threshold PMOS transistor having one end connected to the first supply power voltage, the other end connected to the output port of the second switch, and a gate connected to an output port of the fourth switch, and/or a second low-threshold PMOS transistor having one end connected to the first supply power voltage, the other end connected to the output port of the fourth switch, and a gate connected to the output port of the second inverter.
In an eighth embodiment of the CP flip-flop according to the present invention, the clock delay unit may include a fourth inverter for inverting the clock signal, a fifth inverter for inverting an output signal of the fourth inverter, and a NOR gate for inverting and delaying the clock signal and outputting an inverted clock signal in response to an output signal of the fifth inverter and an anti-floating signal. The fourth and fifth inverters include low-threshold MOS transistors. The NOR gate includes low-threshold MOS transistors and high-threshold MOS transistors. The same switch unit and latch unit as in the seventh embodiment are applied.
In a ninth embodiment of the CP flip-flop according to the present invention, the CP flip-flop may further comprise a data holding unit. The data holding unit may include: a first high-threshold NMOS transistor having one end connected to an output port of the second switch and a gate to which the data hold signal is applied; a second high-threshold NMOS transistor having one end connected to an output port of the fourth switch and a gate to which the data hold signal is applied; a second inverter having an input port connected to the other end of the first high-threshold NMOS transistor and an output port connected to the other end of the second high-threshold NMOS transistor; and a third inverter having an input port connected to the other end of the second high-threshold NMOS transistor and an output port connected to the other end of the first high-threshold NMOS transistor.
In this case, the latch unit may include: a first inverter having an input port connected to an output port of the second switch and an output port connected to an output port of the fourth switch; and a second inverter having an input port connected to an output port of the fourth switch and an output port connected to the output port of the second switch. Each of the first and second inverters may include high-threshold MOS transistors.
The latch unit may further comprise a first low-threshold PMOS transistor having one end connected to the first supply power voltage, the other end connected to the output port of the second switch, and a gate connected to the output port of the fourth switch, and/or a second low-threshold PMOS transistor having one end connected to the first supply power voltage, the other end connected to the output port of the fourth switch, and a gate connected to the output port of the second inverter. The third inverter for inverting the data signal and the switch unit, which are the same as those of the seventh embodiment, are applied.
In a tenth embodiment of the present invention, the CP flip-flop may further comprise a reset unit. The reset unit may comprise: a first NAND gate that responds to set and reset signals; a first high-threshold NMOS transistor having one end connected to the output port of the second switch and a gate to which the reset signal is applied; a second high-threshold NMOS transistor having one end connected to the output port of the fourth switch, the other end connected to the other end of the first high-threshold NMOS transistor, and a gate to which the set signal is applied; and a third high-threshold NMOS transistor having one end connected to the second power supply voltage, the other end connected to the other ends of the first and second high-threshold NMOS transistors, and a gate to which an output signal of the first NAND gate is applied. The first NAND gate may include a first low-threshold MOS transistor.
In this case, the clock delay unit may include a fourth inverter for inverting the clock signal, a second NAND gate that responds to an output signal of the fourth inverter and an enable signal, and a NOR gate that responds to an output signal of the second NAND gate and the anti-floating signal. The switch unit, the latch unit, and the third inverter, which are the same as in the seventh embodiment, are applied.